Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
6,788 |
54,576 |
12% |
|
Number used as Flip Flops |
6,781 |
|
|
|
Number used as Latches |
1 |
|
|
|
Number used as Latch-thrus |
6 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
7,336 |
27,288 |
26% |
|
Number used as logic |
5,521 |
27,288 |
20% |
|
Number using O6 output only |
4,029 |
|
|
|
Number using O5 output only |
409 |
|
|
|
Number using O5 and O6 |
1,083 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
590 |
6,408 |
9% |
|
Number used as Dual Port RAM |
336 |
|
|
|
Number using O6 output only |
36 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
300 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
254 |
|
|
|
Number using O6 output only |
105 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
149 |
|
|
|
Number used exclusively as route-thrus |
1,225 |
|
|
|
Number with same-slice register load |
1,195 |
|
|
|
Number with same-slice carry load |
30 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
2,658 |
6,822 |
38% |
|
Number of LUT Flip Flop pairs used |
7,531 |
|
|
|
Number with an unused Flip Flop |
2,738 |
7,531 |
36% |
|
Number with an unused LUT |
195 |
7,531 |
2% |
|
Number of fully used LUT-FF pairs |
4,598 |
7,531 |
61% |
|
Number of unique control sets |
485 |
|
|
|
Number of slice register sites lost to control set restrictions |
2,147 |
54,576 |
3% |
|
Number of bonded IOBs |
165 |
296 |
55% |
|
Number of LOCed IOBs |
165 |
165 |
100% |
|
IOB Flip Flops |
20 |
|
|
|
IOB Master Pads |
1 |
|
|
|
IOB Slave Pads |
1 |
|
|
|
Number of bonded IPADs |
10 |
16 |
62% |
|
Number of bonded OPADs |
6 |
8 |
75% |
|
Number of RAMB16BWERs |
72 |
116 |
62% |
|
Number of RAMB8BWERs |
1 |
232 |
1% |
|
Number of BUFIO2/BUFIO2_2CLKs |
4 |
32 |
12% |
|
Number used as BUFIO2s |
4 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
13 |
16 |
81% |
|
Number used as BUFGs |
13 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
1 |
8 |
12% |
|
Number used as DCMs |
1 |
|
|
|
Number used as DCM_CLKGENs |
0 |
|
|
|
Number of ILOGIC2/ISERDES2s |
4 |
376 |
1% |
|
Number used as ILOGIC2s |
4 |
|
|
|
Number used as ISERDES2s |
0 |
|
|
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
24 |
376 |
6% |
|
Number used as IODELAY2s |
0 |
|
|
|
Number used as IODRP2s |
2 |
|
|
|
Number used as IODRP2_MCBs |
22 |
|
|
|
Number of OLOGIC2/OSERDES2s |
60 |
376 |
15% |
|
Number used as OLOGIC2s |
16 |
|
|
|
Number used as OSERDES2s |
44 |
|
|
|
Number of BSCANs |
1 |
4 |
25% |
|
Number of BUFHs |
0 |
256 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
1 |
4 |
25% |
|
Number of DSP48A1s |
0 |
58 |
0% |
|
Number of GTPA1_DUALs |
2 |
2 |
100% |
|
Number of LOCed GTPA1_DUALs |
1 |
2 |
50% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
1 |
2 |
50% |
|
Number of PCIE_A1s |
1 |
1 |
100% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
4 |
4 |
100% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Number of RPM macros |
12 |
|
|
|
Average Fanout of Non-Clock Nets |
3.62 |
|
|
|