isesynth Project Status
Project File: isesynth.ise Implementation State: New
Module Name: xilinx_pcie_1_1_ep_s6
  • Errors:
 
Target Device: xc6slx45t-3fgg484
  • Warnings:
 
Product Version:ISE 11.4
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 09/15/2010 - 21:27:23