Core Statistics |
Core Type=s6_gtpwizard_v1_3 |
gtp0_protocol_file=pcie |
gtp1_protocol_file=Use_GTP0_settings |
Core Type=fifo_generator_v6_1 |
c_common_clock=0 |
c_data_count_width=15 |
c_din_width=8 |
c_dout_rst_val=0 |
c_dout_width=32 |
c_enable_rst_sync=1 |
c_error_injection_type=0 |
c_full_flags_rst_val=0 |
c_has_almost_empty=0 |
c_has_almost_full=0 |
c_has_data_count=0 |
c_has_int_clk=0 |
c_has_overflow=0 |
c_has_rd_data_count=0 |
c_has_rst=1 |
c_has_srst=0 |
c_has_underflow=1 |
c_has_valid=0 |
c_has_wr_ack=0 |
c_has_wr_data_count=0 |
c_implementation_type=2 |
c_memory_type=1 |
c_msgon_val=1 |
c_overflow_low=0 |
c_preload_latency=1 |
c_preload_regs=0 |
c_prim_fifo_type=8kx4 |
c_prog_empty_thresh_assert_val=2 |
c_prog_empty_thresh_negate_val=3 |
c_prog_empty_type=0 |
c_prog_full_thresh_assert_val=32765 |
c_prog_full_thresh_negate_val=32764 |
c_prog_full_type=0 |
c_rd_data_count_width=13 |
c_rd_depth=8192 |
c_rd_freq=1 |
c_rd_pntr_width=13 |
c_underflow_low=0 |
c_use_dout_rst=1 |
c_use_ecc=0 |
c_use_embedded_reg=0 |
c_use_fwft_data_count=0 |
c_valid_low=0 |
c_wr_ack_low=0 |
c_wr_data_count_width=15 |
c_wr_depth=32768 |
c_wr_freq=1 |
c_wr_pntr_width=15 |
Core Type=selectio_wiz_v1_2 |
active_edge=BOTH_RISE_FALL |
bus_dir=INPUTS |
bus_in_delay=NONE |
bus_io_std=LVDS_33 |
bus_out_delay=NONE |
bus_sig_type=DIFF |
clk_buf=BUFIO2 |
clk_delay=NONE |
clk_io_std=LVDS_33 |
clk_sig_type=DIFF |
enable_bitslip=false |
enable_train=false |
serialization_factor=8 |
system_data_width=6 |
use_serialization=false |
Core Type=aurora_8b10b_v5_1 |
backchannel_mode=Sidebands |
c_aurora_lanes=2 |
c_column_used=None |
c_gt_clock_1=GTPD1 |
c_gt_clock_2=None |
c_gt_loc_1=X |
c_gt_loc_10=X |
c_gt_loc_11=X |
c_gt_loc_12=X |
c_gt_loc_13=X |
c_gt_loc_14=X |
c_gt_loc_15=X |
c_gt_loc_16=X |
c_gt_loc_17=X |
c_gt_loc_18=X |
c_gt_loc_19=X |
c_gt_loc_2=X |
c_gt_loc_20=X |
c_gt_loc_21=X |
c_gt_loc_22=X |
c_gt_loc_23=X |
c_gt_loc_24=X |
c_gt_loc_25=X |
c_gt_loc_26=X |
c_gt_loc_27=X |
c_gt_loc_28=X |
c_gt_loc_29=X |
c_gt_loc_3=1 |
c_gt_loc_30=X |
c_gt_loc_31=X |
c_gt_loc_32=X |
c_gt_loc_33=X |
c_gt_loc_34=X |
c_gt_loc_35=X |
c_gt_loc_36=X |
c_gt_loc_37=X |
c_gt_loc_38=X |
c_gt_loc_39=X |
c_gt_loc_4=2 |
c_gt_loc_40=X |
c_gt_loc_41=X |
c_gt_loc_42=X |
c_gt_loc_43=X |
c_gt_loc_44=X |
c_gt_loc_45=X |
c_gt_loc_46=X |
c_gt_loc_47=X |
c_gt_loc_48=X |
c_gt_loc_5=X |
c_gt_loc_6=X |
c_gt_loc_7=X |
c_gt_loc_8=X |
c_gt_loc_9=X |
c_lane_width=2 |
c_line_rate=1.5 |
c_nfc=true |
c_nfc_mode=COMP |
c_refclk_frequency=75.0 |
c_simplex=false |
c_simplex_mode=TX |
c_stream=false |
c_ufc=false |
dataflow_config=Duplex |
flow_mode=Completion_NFC |
interface_mode=Framing |
Core Type=blk_mem_gen_v4_1 |
c_addra_width=9 |
c_addrb_width=9 |
c_algorithm=1 |
c_byte_size=9 |
c_common_clk=1 |
c_default_data=0 |
c_disable_warn_bhv_coll=0 |
c_disable_warn_bhv_range=0 |
c_has_ena=0 |
c_has_enb=0 |
c_has_injecterr=0 |
c_has_mem_output_regs_a=0 |
c_has_mem_output_regs_b=0 |
c_has_mux_output_regs_a=0 |
c_has_mux_output_regs_b=0 |
c_has_regcea=0 |
c_has_regceb=0 |
c_has_rsta=0 |
c_has_rstb=0 |
c_init_file_name=no_coe_file_loaded |
c_inita_val=0 |
c_initb_val=0 |
c_load_init_file=0 |
c_mem_type=1 |
c_mux_pipeline_stages=0 |
c_prim_type=1 |
c_read_depth_a=512 |
c_read_depth_b=512 |
c_read_width_a=32 |
c_read_width_b=32 |
c_rst_priority_a=CE |
c_rst_priority_b=CE |
c_rst_type=SYNC |
c_rstram_a=0 |
c_rstram_b=0 |
c_sim_collision_check=ALL |
c_use_byte_wea=0 |
c_use_byte_web=0 |
c_use_default_data=0 |
c_use_ecc=0 |
c_wea_width=1 |
c_web_width=1 |
c_write_depth_a=512 |
c_write_depth_b=512 |
c_write_mode_a=READ_FIRST |
c_write_mode_b=READ_FIRST |
c_write_width_a=32 |
c_write_width_b=32 |
Core Type=memco |
LANGUAGE=VHDL |
NO_OF_CONTROLLERS=1 |
SYNTHESIS_TOOL=XST |
mcb3_CALIB_SOFT_IP=TRUE |
mcb3_CAS_LATENCY=4 |
mcb3_MEM_ADDR_ORDER=BANK_ROW_COLUMN |
mcb3_MEM_ADDR_WIDTH=13 |
mcb3_MEM_BANKADDR_WIDTH=2 |
mcb3_MEM_BURST_LEN=4 |
mcb3_MEM_DDR1_2_ODS=FULL |
mcb3_MEM_DDR2_3_HIGH_TEMP_SR=NORMAL |
mcb3_MEM_DDR2_DIFF_DQS_EN=YES |
mcb3_MEM_DDR2_RTT=50OHMS |
mcb3_MEM_DENSITY=512Mb |
mcb3_MEM_INTERFACE_TYPE=DDR2_SDRAM |
mcb3_MEM_NUM_COL_BITS=10 |
mcb3_MEM_TRAS=45000 |
mcb3_MEM_TRCD=12500 |
mcb3_MEM_TREFI=7800000 |
mcb3_MEM_TRFC=105000 |
mcb3_MEM_TRP=12500 |
mcb3_MEM_TRTP=7500 |
mcb3_MEM_TWR=15000 |
mcb3_MEM_TWTR=7500 |
mcb3_MEM_TYPE=DDR2 |
mcb3_NUM_DQ_PINS=16 |
Core Type=mig_v3_4 |
INTERFACE_TYPE=DDR2_SDRAM |
LANGUAGE=VHDL |
SYNTHESIS_TOOL=XST |
mcb3_CALIB_SOFT_IP=TRUE |
mcb3_CAS_LATENCY=4 |
mcb3_MEM_ADDR_ORDER=BANK_ROW_COLUMN |
mcb3_MEM_ADDR_WIDTH=13 |
mcb3_MEM_BANKADDR_WIDTH=2 |
mcb3_MEM_BURST_LEN=4 |
mcb3_MEM_DDR1_2_ODS=FULL |
mcb3_MEM_DDR2_3_HIGH_TEMP_SR=NORMAL |
mcb3_MEM_DDR2_DIFF_DQS_EN=YES |
mcb3_MEM_DDR2_RTT=50OHMS |
mcb3_MEM_DENSITY=512Mb |
mcb3_MEM_INTERFACE_TYPE=DDR2_SDRAM |
mcb3_MEM_NUM_COL_BITS=10 |
mcb3_MEM_TRAS=45000 |
mcb3_MEM_TRCD=12500 |
mcb3_MEM_TREFI=7800000 |
mcb3_MEM_TRFC=105000 |
mcb3_MEM_TRP=12500 |
mcb3_MEM_TRTP=7500 |
mcb3_MEM_TWR=15000 |
mcb3_MEM_TWTR=7500 |
mcb3_MEM_TYPE=DDR2 |
mcb3_NUM_DQ_PINS=16 |
Core Type=blk_mem_gen_v3_3 |
c_addra_width=14 |
c_addrb_width=15 |
c_algorithm=1 |
c_byte_size=9 |
c_common_clk=0 |
c_default_data=0 |
c_disable_warn_bhv_coll=1 |
c_disable_warn_bhv_range=0 |
c_has_ena=1 |
c_has_enb=1 |
c_has_injecterr=0 |
c_has_mem_output_regs_a=0 |
c_has_mem_output_regs_b=0 |
c_has_mux_output_regs_a=0 |
c_has_mux_output_regs_b=0 |
c_has_regcea=0 |
c_has_regceb=0 |
c_has_rsta=0 |
c_has_rstb=0 |
c_init_file_name=no_coe_file_loaded |
c_inita_val=0 |
c_initb_val=0 |
c_load_init_file=0 |
c_mem_type=2 |
c_mux_pipeline_stages=0 |
c_prim_type=1 |
c_read_depth_a=16384 |
c_read_depth_b=32768 |
c_read_width_a=32 |
c_read_width_b=16 |
c_rst_priority_a=CE |
c_rst_priority_b=CE |
c_rst_type=SYNC |
c_rstram_a=0 |
c_rstram_b=0 |
c_sim_collision_check=ALL |
c_use_byte_wea=0 |
c_use_byte_web=0 |
c_use_default_data=0 |
c_use_ecc=0 |
c_wea_width=1 |
c_web_width=1 |
c_write_depth_a=16384 |
c_write_depth_b=32768 |
c_write_mode_a=READ_FIRST |
c_write_mode_b=READ_FIRST |
c_write_width_a=32 |
c_write_width_b=16 |
Core Type=fifo_generator_v6_1 |
c_common_clock=0 |
c_data_count_width=4 |
c_din_width=32 |
c_dout_rst_val=0 |
c_dout_width=32 |
c_enable_rst_sync=1 |
c_error_injection_type=0 |
c_full_flags_rst_val=0 |
c_has_almost_empty=0 |
c_has_almost_full=0 |
c_has_data_count=0 |
c_has_int_clk=0 |
c_has_overflow=1 |
c_has_rd_data_count=0 |
c_has_rst=1 |
c_has_srst=0 |
c_has_underflow=1 |
c_has_valid=0 |
c_has_wr_ack=0 |
c_has_wr_data_count=0 |
c_implementation_type=2 |
c_memory_type=2 |
c_msgon_val=1 |
c_overflow_low=0 |
c_preload_latency=1 |
c_preload_regs=0 |
c_prim_fifo_type=512x36 |
c_prog_empty_thresh_assert_val=2 |
c_prog_empty_thresh_negate_val=3 |
c_prog_empty_type=0 |
c_prog_full_thresh_assert_val=13 |
c_prog_full_thresh_negate_val=12 |
c_prog_full_type=0 |
c_rd_data_count_width=4 |
c_rd_depth=16 |
c_rd_freq=1 |
c_rd_pntr_width=4 |
c_underflow_low=0 |
c_use_dout_rst=1 |
c_use_ecc=0 |
c_use_embedded_reg=0 |
c_use_fwft_data_count=0 |
c_valid_low=0 |
c_wr_ack_low=0 |
c_wr_data_count_width=4 |
c_wr_depth=16 |
c_wr_freq=1 |
c_wr_pntr_width=4 |
Core Type=chipscope_icon_v1_04_a |
c_build_revision=0 |
c_core_major_ver=1 |
c_core_minor_alpha_ver=97 |
c_core_minor_ver=2 |
c_core_type=1 |
c_major_version=12 |
c_mfg_id=1 |
c_minor_version=1 |
c_num_control_ports=1 |
c_part_idcode_register=0 |
c_use_bufr=0 |
c_use_control0=1 |
c_use_control1=0 |
c_use_control10=0 |
c_use_control11=0 |
c_use_control12=0 |
c_use_control13=0 |
c_use_control14=0 |
c_use_control2=0 |
c_use_control3=0 |
c_use_control4=0 |
c_use_control5=0 |
c_use_control6=0 |
c_use_control7=0 |
c_use_control8=0 |
c_use_control9=0 |
c_use_ext_bscan=0 |
c_use_jtag_bufg=1 |
c_use_new_parser=0 |
c_use_sim=0 |
c_use_softbscan=0 |
c_use_unused_bscan=0 |
c_use_xst_tck_workaround=1 |
c_user_scan_chain=1 |
c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false |
c_xdevicefamily=spartan6 |
Core Type=chipscope_ila_v1_03_a |
c_build_revision=0 |
c_core_major_ver=1 |
c_core_minor_alpha_ver=97 |
c_core_minor_ver=2 |
c_core_type=2 |
c_data_depth=1024 |
c_data_width=259 |
c_ext_cap_pin_mode=0 |
c_ext_cap_rate_mode=0 |
c_ext_cap_use_reg=1 |
c_m0_tpid=0 |
c_m0_type=0 |
c_m10_tpid=10 |
c_m10_type=0 |
c_m11_tpid=11 |
c_m11_type=0 |
c_m12_tpid=12 |
c_m12_type=0 |
c_m13_tpid=13 |
c_m13_type=0 |
c_m14_tpid=14 |
c_m14_type=0 |
c_m15_tpid=15 |
c_m15_type=0 |
c_m1_tpid=1 |
c_m1_type=0 |
c_m2_tpid=2 |
c_m2_type=0 |
c_m3_tpid=3 |
c_m3_type=0 |
c_m4_tpid=4 |
c_m4_type=0 |
c_m5_tpid=5 |
c_m5_type=0 |
c_m6_tpid=6 |
c_m6_type=0 |
c_m7_tpid=7 |
c_m7_type=0 |
c_m8_tpid=8 |
c_m8_type=0 |
c_m9_tpid=9 |
c_m9_type=0 |
c_major_version=12 |
c_mcnt0_width=1 |
c_mcnt10_width=1 |
c_mcnt11_width=1 |
c_mcnt12_width=1 |
c_mcnt13_width=1 |
c_mcnt14_width=1 |
c_mcnt15_width=1 |
c_mcnt1_width=1 |
c_mcnt2_width=1 |
c_mcnt3_width=1 |
c_mcnt4_width=1 |
c_mcnt5_width=1 |
c_mcnt6_width=1 |
c_mcnt7_width=1 |
c_mcnt8_width=1 |
c_mcnt9_width=1 |
c_mfg_id=1 |
c_minor_version=1 |
c_num_ext_cap_pins=8 |
c_num_match_units=4 |
c_num_tseq_cnt=0 |
c_num_tseq_states=1 |
c_ram_type=1 |
c_srl16_type=2 |
c_tc_mcnt_width=1 |
c_timestamp_depth=512 |
c_timestamp_type=0 |
c_timestamp_width=32 |
c_trig0_width=1 |
c_trig10_width=1 |
c_trig11_width=1 |
c_trig12_width=1 |
c_trig13_width=1 |
c_trig14_width=1 |
c_trig15_width=1 |
c_trig1_width=1 |
c_trig2_width=1 |
c_trig3_width=1 |
c_trig4_width=1 |
c_trig5_width=1 |
c_trig6_width=1 |
c_trig7_width=1 |
c_trig8_width=1 |
c_trig9_width=1 |
c_tseq_cnt0_width=1 |
c_tseq_cnt1_width=1 |
c_tseq_type=0 |
c_use_atc_clkin=0 |
c_use_data=1 |
c_use_gap=0 |
c_use_inv_clk=0 |
c_use_mcnt0=0 |
c_use_mcnt1=0 |
c_use_mcnt10=0 |
c_use_mcnt11=0 |
c_use_mcnt12=0 |
c_use_mcnt13=0 |
c_use_mcnt14=0 |
c_use_mcnt15=0 |
c_use_mcnt2=0 |
c_use_mcnt3=0 |
c_use_mcnt4=0 |
c_use_mcnt5=0 |
c_use_mcnt6=0 |
c_use_mcnt7=0 |
c_use_mcnt8=0 |
c_use_mcnt9=0 |
c_use_rpm=1 |
c_use_storage_qual=1 |
c_use_tc_mcnt=0 |
c_use_trig0=1 |
c_use_trig1=1 |
c_use_trig10=0 |
c_use_trig11=0 |
c_use_trig12=0 |
c_use_trig13=0 |
c_use_trig14=0 |
c_use_trig15=0 |
c_use_trig2=1 |
c_use_trig3=1 |
c_use_trig4=0 |
c_use_trig5=0 |
c_use_trig6=0 |
c_use_trig7=0 |
c_use_trig8=0 |
c_use_trig9=0 |
c_use_trig_out=0 |
c_use_trigdata0=0 |
c_use_trigdata1=0 |
c_use_trigdata10=0 |
c_use_trigdata11=0 |
c_use_trigdata12=0 |
c_use_trigdata13=0 |
c_use_trigdata14=0 |
c_use_trigdata15=0 |
c_use_trigdata2=0 |
c_use_trigdata3=0 |
c_use_trigdata4=0 |
c_use_trigdata5=0 |
c_use_trigdata6=0 |
c_use_trigdata7=0 |
c_use_trigdata8=0 |
c_use_trigdata9=0 |
c_xco_list=Component_Name=ila_pro_0;Number_Of_Trigger_Ports=4;Max_Sequence_Levels=1;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=1024;Enable_Storage_Qualification=true;Data_Same_As_Trigger=false;Data_Port_Width=259;Trigger_Port_Width_1=1;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic;Exclude_From_Data_Storage_1=true;Trigger_Port_Width_2=1;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic;Exclude_From_Data_Storage_2=true;Trigger_Port_Width_3=1;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic;Exclude_From_Data_Storage_3=true;Trigger_Port_Width_4=1;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic;Exclude_From_Data_Storage_4=true;Trigger_Port_Width_5=1;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic;Exclude_From_Data_Storage_5=true;Trigger_Port_Width_6=1;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic;Exclude_From_Data_Storage_6=true;Trigger_Port_Width_7=1;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic;Exclude_From_Data_Storage_7=true;Trigger_Port_Width_8=1;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic;Exclude_From_Data_Storage_8=true;Trigger_Port_Width_9=1;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic;Exclude_From_Data_Storage_9=true;Trigger_Port_Width_10=1;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic;Exclude_From_Data_Storage_10=true;Trigger_Port_Width_11=1;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic;Exclude_From_Data_Storage_11=true;Trigger_Port_Width_12=1;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic;Exclude_From_Data_Storage_12=true;Trigger_Port_Width_13=1;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic;Exclude_From_Data_Storage_13=true;Trigger_Port_Width_14=1;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic;Exclude_From_Data_Storage_14=true;Trigger_Port_Width_15=1;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic;Exclude_From_Data_Storage_15=true;Trigger_Port_Width_16=1;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic;Exclude_From_Data_Storage_16=true |
c_xdevicefamily=spartan6 |
Core Type=s6_pcie_v1_2 |
BAR0=F0000000 |
BAR1=00000000 |
BAR2=00000000 |
BAR3=00000000 |
BAR4=00000000 |
BAR5=00000000 |
CARDBUS_CIS_POINTER=00000000 |
CFG_DEV_ID=ABCD |
CFG_REV_ID=00 |
CFG_SUBSYS_ID=1234 |
CFG_SUBSYS_VEN_ID=10EE |
CFG_VEN_ID=10EE |
CLASS_CODE=068000 |
DEV_CAP_ENDPOINT_L0S_LATENCY=7 |
DEV_CAP_ENDPOINT_L1_LATENCY=7 |
DEV_CAP_EXT_TAG_SUPPORTED=FALSE |
DEV_CAP_MAX_PAYLOAD_SUPPORTED=2 |
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0 |
DISABLE_SCRAMBLING=FALSE |
ENABLE_RX_TD_ECRC_TRIM=FALSE |
EXPANSION_ROM=000000 |
GTP_SEL=0 |
LINK_CAP_ASPM_SUPPORT=1 |
LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE |
MSI_CAP_MULTIMSGCAP=0 |
MSI_CAP_MULTIMSG_EXTENSION=0 |
PCIE_CAP_CAPABILITY_VERSION=1 |
PCIE_CAP_DEVICE_PORT_TYPE=1 |
PCIE_GENERIC=000010101111 |
PM_CAP_D1SUPPORT=TRUE |
PM_CAP_D2SUPPORT=TRUE |
PM_CAP_DSI=FALSE |
PM_CAP_PMESUPPORT=0F |
PM_DATA0=04 |
PM_DATA1=00 |
PM_DATA2=00 |
PM_DATA3=00 |
PM_DATA4=04 |
PM_DATA5=00 |
PM_DATA6=00 |
PM_DATA7=00 |
PM_DATA_SCALE0=0 |
PM_DATA_SCALE1=0 |
PM_DATA_SCALE2=0 |
PM_DATA_SCALE3=0 |
PM_DATA_SCALE4=0 |
PM_DATA_SCALE5=0 |
PM_DATA_SCALE6=0 |
PM_DATA_SCALE7=0 |
REF_CLK_FREQ=0 |
TL_RX_RAM_RADDR_LATENCY=0 |
TL_RX_RAM_RDATA_LATENCY=2 |
TL_RX_RAM_WRITE_LATENCY=0 |
TL_TX_RAM_RADDR_LATENCY=0 |
TL_TX_RAM_RDATA_LATENCY=2 |
USR_CFG=FALSE |
USR_EXT_CFG=FALSE |
VC0_CPL_INFINITE=TRUE |
VC0_RX_RAM_LIMIT=7FF |
VC0_TOTAL_CREDITS_CD=211 |
VC0_TOTAL_CREDITS_CH=40 |
VC0_TOTAL_CREDITS_NPH=8 |
VC0_TOTAL_CREDITS_PD=211 |
VC0_TOTAL_CREDITS_PH=32 |
VC0_TX_LASTPACKET=14 |
Core Type=clk_wiz_v1_4 |
clkin1_period=40.0 |
clkin2_period=40.0 |
diff_ext_feedback=false |
feedback_source=FDBK_AUTO |
num_out_clk=1 |
primtype_sel=PLL_BASE |
use_dyn_phase_shift=false |
use_dyn_reconfig=false |
use_inclk_switchover=false |
use_max_i_jitter=true |
use_min_o_jitter=false |
use_phase_alignment=false |
use_power_down=false |
Core Type=clk_wiz_v1_5 |
clkin1_period=40.0 |
clkin2_period=40.0 |
feedback_source=FDBK_AUTO |
num_out_clk=1 |
primtype_sel=DCM_SP |
use_dyn_phase_shift=false |
use_dyn_reconfig=false |
use_inclk_switchover=false |
use_max_i_jitter=false |
use_min_o_jitter=false |
use_phase_alignment=false |
use_power_down=false |