Environment Settings | ||||
Environment Variable | xst | ngdbuild | map | par |
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
Path | C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Actel\Libero_v9.0\Model\win32acoem; C:\Actel\Libero_v9.0\Designer\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\OrCAD\OrCAD_16.3_Demo\tools\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library; C:\OrCAD\OrCAD_16.3_Demo\tools\Capture; C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin; C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt; C:\Program Files\Altium Designer 6\System; O:\Hardtool; C:\Elmer6.2\lib; C:\Elmer6.2\bin |
C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Actel\Libero_v9.0\Model\win32acoem; C:\Actel\Libero_v9.0\Designer\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\OrCAD\OrCAD_16.3_Demo\tools\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library; C:\OrCAD\OrCAD_16.3_Demo\tools\Capture; C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin; C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt; C:\Program Files\Altium Designer 6\System; O:\Hardtool; C:\Elmer6.2\lib; C:\Elmer6.2\bin |
C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Actel\Libero_v9.0\Model\win32acoem; C:\Actel\Libero_v9.0\Designer\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\OrCAD\OrCAD_16.3_Demo\tools\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library; C:\OrCAD\OrCAD_16.3_Demo\tools\Capture; C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin; C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt; C:\Program Files\Altium Designer 6\System; O:\Hardtool; C:\Elmer6.2\lib; C:\Elmer6.2\bin |
C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Actel\Libero_v9.0\Model\win32acoem; C:\Actel\Libero_v9.0\Designer\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\OrCAD\OrCAD_16.3_Demo\tools\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice; C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library; C:\OrCAD\OrCAD_16.3_Demo\tools\Capture; C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin; C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin; C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt; C:\Program Files\Altium Designer 6\System; O:\Hardtool; C:\Elmer6.2\lib; C:\Elmer6.2\bin |
XILINX | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE |
XILINX_DSP | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE |
XILINX_EDK | C:\Xilinx\12.1\ISE_DS\EDK | C:\Xilinx\12.1\ISE_DS\EDK | C:\Xilinx\12.1\ISE_DS\EDK | C:\Xilinx\12.1\ISE_DS\EDK |
XILINX_PLANAHEAD | C:\Xilinx\12.1\ISE_DS\PlanAhead | C:\Xilinx\12.1\ISE_DS\PlanAhead | C:\Xilinx\12.1\ISE_DS\PlanAhead | C:\Xilinx\12.1\ISE_DS\PlanAhead |
XIL_TIMING_ALLOW_IMPOSSIBLE | 1 | 1 | 1 | 1 |
Synthesis Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-ifn | s6bf_board_top.prj | ||
-ifmt | mixed | Mixed | |
-ofn | s6bf_board_top | ||
-ofmt | NGC | NGC | |
-p | xc6slx45t-2-fgg484 | ||
-top | s6bf_board_top | ||
-opt_mode | Optimization Goal | Speed | Speed |
-opt_level | Optimization Effort | 1 | 1 |
-power | Power Reduction | NO | No |
-iuc | Use synthesis Constraints File | NO | No |
-lso | Library Search Order | s6bf_board_top.lso | |
-keep_hierarchy | Keep Hierarchy | YES | No |
-netlist_hierarchy | Netlist Hierarchy | as_optimized | As_Optimized |
-rtlview | Generate RTL Schematic | Yes | No |
-glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
-read_cores | Read Cores | YES | Yes |
-sd | Cores Search Directories | {"User_coregen_NGC_copied" } | |
-write_timing_constraints | Write Timing Constraints | YES | No |
-cross_clock_analysis | Cross Clock Analysis | NO | No |
-bus_delimiter | Bus Delimiter | <> | <> |
-slice_utilization_ratio | Slice Utilization Ratio | 100 | 100 |
-bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100 |
-dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100 |
-reduce_control_sets | auto | Auto | |
-fsm_extract | YES | Yes | |
-fsm_encoding | User | Auto | |
-safe_implementation | No | No | |
-fsm_style | lut | LUT | |
-ram_extract | Yes | Yes | |
-ram_style | Auto | Auto | |
-rom_extract | Yes | Yes | |
-shreg_extract | YES | Yes | |
-rom_style | Auto | Auto | |
-auto_bram_packing | NO | No | |
-resource_sharing | YES | Yes | |
-async_to_sync | NO | No | |
-use_dsp48 | auto | Auto | |
-iobuf | YES | Yes | |
-max_fanout | 100000 | 100000 | |
-bufg | 16 | 16 | |
-register_duplication | YES | Yes | |
-register_balancing | No | No | |
-optimize_primitives | NO | No | |
-use_clock_enable | Auto | Auto | |
-use_sync_set | Auto | Auto | |
-use_sync_reset | Auto | Auto | |
-iob | false | Auto | |
-equivalent_register_removal | NO | Yes | |
-slice_utilization_ratio_maxmargin | 5 | 0 |
Translation Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-aul | Allow Unmatched LOC Constraints | true | false |
-aut | Allow Unmatched Timing Group Constraints | true | false |
-intstyle | ise | None | |
-dd | _ngo | None | |
-p | xc6slx45t-fgg484-2 | None | |
-sd | Macro Search Path | User_coregen_NGC_copied | None |
-uc | User_Constraints/s6bf_board_TIMING-constraints.ucf | None |
Map Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-detail | Generate Detailed MAP Report | TRUE | TRUE |
-ol | Place & Route Effort Level (Overall) | high | high |
-ir | Use RLOC Constraints | OFF | OFF |
-t | Starting Placer Cost Table (1-100) Map | 1 | 0 |
-intstyle | ise | None | |
-lc | LUT Combining | off | off |
-o | s6bf_board_top_map.ncd | None | |
-w | true | false | |
-pr | Pack I/O Registers/Latches into IOBs | off | off |
-p | xc6slx45t-fgg484-2 | None |
Place and Route Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-intstyle | ise | ||
-ol | Place & Route Effort Level (Overall) | high | std |
-w | true | false |
Operating System Information | ||||
Operating System Information | xst | ngdbuild | map | par |
CPU Architecture/Speed | Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz/2660 MHz | Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz/2660 MHz | Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz/2660 MHz | Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz/2660 MHz |
Host | inagy | inagy | inagy | inagy |
OS Name | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional |
OS Release | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) |