s6bf_board_top Project Status
Project File: s6bf_1.xise Parser Errors: No Errors
Module Name: s6bf_board_top Implementation State: Translated
Target Device: xc6slx45t-2fgg484
  • Errors:
X 40 Errors (1 new)
Product Version:ISE 12.1
  • Warnings:
2261 Warnings (2028 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 2691 54576 4%
Number of Slice LUTs 3151 27288 11%
Number of fully used LUT-FF pairs 1372 4470 30%
Number of bonded IOBs 153 296 51%
Number of Block RAM/FIFO 8 116 6%
Number of BUFG/BUFGCTRLs 10 16 62%
Number of DSP48A1s 1 58 1%
Number of PLL_ADVs 4 4 100%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu 11. Nov 21:30:36 201002028 Warnings (2028 new)329 Infos (329 new)
Translation ReportCurrentThu 11. Nov 21:37:20 2010X 40 Errors (1 new)233 Warnings (0 new)7 Infos (0 new)
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 11/11/2010 - 21:40:07