FPGA IP core designs

Year: 2007-2019

I have released several IP core designs for FPGAs as free and open source projects, on the opencores.org website.

These are all imterface controller logic blocks.

• OP2P (OpenPeerToPeer Interface)

Custom packet-based protocol for point to point DMA transfers over cable.

• PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)

TLP packet decoding/encoding layer to be used with the Xilinx Spartan-6 PCIe hard IP.

• PCIe_mini_axi4s_wb

TLP packet decoding/encoding layer to be used with the Xilinx Kintex/Virtex hard IP.

• pci_mini

PCI (parallel 32-bit) to Wishbone bridge.

• Super-I/O (SIO) controller

SIO controller chip replacement logic.