Pci_mini :  PCI target to Wishbone bridge IP core

Year: 2007


  Tis is an IP core used on FPGAs, for connecting 2 local buses: one PCI and one Wishbone.

The project is fully open-source, and written in verilog language. (one single file, so easy to use)

Target only on the PCI bus, and master on the Wishbone bus.

The project is available on the WWW.OPENCORES.ORG website too:



The original PCI module is from: Ben Jackson http:www.ben.com/minipci/verilog.php
Redesigned for wishbone : Istvan Nagy (me), PEC Products, Industrial Technologies

Test results:

Synthesis: 279 Slices on Xilinx Spartan-3 FPGA. (14.5% logic on SP3-200k)
Tested on hardware:
-PCI card (with SP2 FPGA) plugged into an old PC with Pentium-II CPU and VIA VT82C693A+VT82C596B chipset
-Custom motherboard developed by me, with the AMD Geode-LX processor, and Spartan-3 FPGA.
Test software: Hardware-Direct.
FPGA project: a peripheral block, consisting: Wishbone intercone module, CAN controller, some custom peripherals, and the PCI2WB bridge.

Download source file and documentation from this site:  LINK